Robert Mustacchi

And so link training is a process of basically figuring out shared... Effectively, what are the shared... ways we're going to operate. So for example, because PCIe is backwards compatible, you can take today's Gen 5 devices and put them in a PCIe Gen 1 board, and the link will train at PCIe Gen 1.

And so link training is a process of basically figuring out shared... Effectively, what are the shared... ways we're going to operate. So for example, because PCIe is backwards compatible, you can take today's Gen 5 devices and put them in a PCIe Gen 1 board, and the link will train at PCIe Gen 1.

You might have a root port that supports up to 16 lanes, but you might put in a NIC that only has one lane, a small 1 gig link. So it will do that. To make these links work at high speeds, is a very complex process because you have to figure out a lot of equalization and tuning so that they can interact.

You might have a root port that supports up to 16 lanes, but you might put in a NIC that only has one lane, a small 1 gig link. So it will do that. To make these links work at high speeds, is a very complex process because you have to figure out a lot of equalization and tuning so that they can interact.

Effectively, link training is this process in this kind of large state machine that basically hopefully ends with the link training, so basically successfully completing the state machine. And it's really done by the PCIe device that you're plugging in and really the PCIe root port, which is

Effectively, link training is this process in this kind of large state machine that basically hopefully ends with the link training, so basically successfully completing the state machine. And it's really done by the PCIe device that you're plugging in and really the PCIe root port, which is

generally a whole bunch of hardware in your CPU that probably itself has a secret core running stuff too that no one tells us about.

generally a whole bunch of hardware in your CPU that probably itself has a secret core running stuff too that no one tells us about.

Yeah, I think that's one part of it. And, you know, that's definitely a large part of it. And other parts of like the digital protocol communication, you know, what features can be used. So, you know, the PCI sake has done a lot of work. And, you know, it's a testament that we can, you know, PCIe has been backwards compatible back to its first release.

Yeah, I think that's one part of it. And, you know, that's definitely a large part of it. And other parts of like the digital protocol communication, you know, what features can be used. So, you know, the PCI sake has done a lot of work. And, you know, it's a testament that we can, you know, PCIe has been backwards compatible back to its first release.

Yeah. Basically, we don't see a device come up. So there's a register in the root port that says, is there a PCI link established? And if you read it, it says no. there sure isn't there sure isn't and you're like well that's very sad um so there was a whole bunch of stuff that we were trying to do to figure this out because you know we had some challenges in the t6 initial initially um

Yeah. Basically, we don't see a device come up. So there's a register in the root port that says, is there a PCI link established? And if you read it, it says no. there sure isn't there sure isn't and you're like well that's very sad um so there was a whole bunch of stuff that we were trying to do to figure this out because you know we had some challenges in the t6 initial initially um

There's some erratum we found the hard way around it needing some double resets and some other conditions. There's a lot of investigation that we kind of split up and kind of took this in a couple different phases. Especially as I think right as this was kind of kicking off, I was disappearing on vacation for a bit.

There's some erratum we found the hard way around it needing some double resets and some other conditions. There's a lot of investigation that we kind of split up and kind of took this in a couple different phases. Especially as I think right as this was kind of kicking off, I was disappearing on vacation for a bit.

But I worked with Nathaniel and Josh and Nathaniel started to basically go through a bunch of, you know, just different questions we had electrically. You know, is there a chance that this could be happening because... because we don't see the device coming out of reset.

But I worked with Nathaniel and Josh and Nathaniel started to basically go through a bunch of, you know, just different questions we had electrically. You know, is there a chance that this could be happening because... because we don't see the device coming out of reset.

So one of the first things we kind of looked at, and now you can correct me where I'm misremembering some of this, was trying to bifurcate, you know, did the device assert it coming out of reset? And did we ever try to even begin PCIe initialization or not? Because depending on the answer to that, that would take us down two very different paths.

So one of the first things we kind of looked at, and now you can correct me where I'm misremembering some of this, was trying to bifurcate, you know, did the device assert it coming out of reset? And did we ever try to even begin PCIe initialization or not? Because depending on the answer to that, that would take us down two very different paths.

And the chip itself has a little pin that says it came out of reset. So there's a bunch of stuff we looked at there. And secondarily, because of a whole bunch of the low-level work we had done to boot, we knew how to read out the state of the PCI state machine diagram that the root port thought it was in. So what this meant is that we could go look at the root port.

And the chip itself has a little pin that says it came out of reset. So there's a bunch of stuff we looked at there. And secondarily, because of a whole bunch of the low-level work we had done to boot, we knew how to read out the state of the PCI state machine diagram that the root port thought it was in. So what this meant is that we could go look at the root port.