.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP016 – FPGA Conference 2023 @keyframes av_boxShadowEffect_av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 16 of the World of FPGA Podcast. It was time for a little trip again. This time I went to Munich to the three-day FPGA conference of PLC2 and the Vogel Verlag. Content of this Episode 3 day FPGA Conference in Munich A little insight My attended lectures Sessions on the first day Linux Build Methodologies: PetaLinux vs. Yocto Flow Coverage (aka Requirement Coverage) Using property descriptions to formally verify FPGA design code Synthesizing a Vivado Project on GitLab-CI and Deploying to an FPGA Board Secure method of enabling multiple design in FPGA Constraining Multiple Clock Domains AMD-Xilinx: Dynamic Function Exchange with Device Tree Overlay GDBServer in Hardware for VexRiscv Processing Systems Next Generation of High-Speed Interfaces for Vision Applications Sessions on the second day Demystify a Vitis Embedded Acceleration Platform MicroBlaze – A most flexible processor for FPGAs and MPSoCs Self organizing administration tool to control FPGA designs Fundamentals of Timing Analysis and Why No FPGA Design Can Do Without It How to crash 100+ AWS FPGA instances and how to insert Trojans into bitstreams Demonstration Setup for HashCache Sessions on the third day Do FPGA designers and hardware designers need to talk? A practical approach to shortening the project timeline How your FPGA design decisions affect PCB board performance Agilex SoC Architecture Turning your FPGA into a fast multichannel ADC PCIe, MIPI CSI-2, HDMI and DDR memory across platforms from an Open Source perspective Constant On-Time (COT) Control for FPGA High-Current Power Supplies Hardware attacks on FPGA: An overview of threats and security mechanisms Next FPGA conference is from July 2nd to 4th, 2024 Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP016 – FPGA Conference 2023 appeared first on World of FPGA by David Kirchner.

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